Power Supply Decoupling Capacitors: Why and Where to Place Them

Understanding power supply decoupling capacitors and where to place them is essential for building stable embedded hardware. As digital microcontrollers switch millions of internal transistors per second, sudden current spikes create high-frequency voltage dips on power supply traces.

1. The physical mechanism of power supply noise

Every PCB trace possesses parasitic inductance (L). Under rapid transient switching, rapid current changes create transient voltage drops across the trace. Without local charge storage, the supply voltage at the chip VDD pin can drop below brownout reset thresholds, causing sudden microcontroller reboots.

2. Sizing ceramic bypass and bulk capacitors

A robust decoupling strategy uses a parallel hierarchy of capacitor values:

• 0.1 uF (100nF) Ceramic: Placed directly at every single VDD pin to filter high-frequency switching transients (10 MHz to 100 MHz).
• 1 uF to 10 uF Tantalum or Ceramic: Placed near the microcontroller to handle mid-frequency demand shifts.
• 100 uF Electrolytic: Placed at the power regulator output to serve as bulk energy storage for transient inductive loads (e.g., relays, WiFi burst transmissions).

3. Critical PCB layout and placement rules

Decoupling capacitors must be positioned as physically close to the chip power pins as possible (under 3mm). Route the capacitor directly between the IC pin and a low-impedance ground plane using separate vias to minimize loop inductance. For microchip comparisons, see our guide on ESP32 vs ESP8266 development[cite: 1].

4. Common decoupling pitfalls

Avoid sharing a single 0.1 uF capacitor across multiple power pins of a multi-pin microcontroller. Each power pin must have its own dedicated ceramic capacitor to prevent inter-pin noise coupling.

When to get help

If you'd rather have this handled directly, see our Hardware & PCB Design Consulting Services for scope and turnaround times.